The present invention relates to an early failure detection system for a multiprocessor system and, more particularly, to an early failure detection system for testing a processor which is idling.
According to a typical conventional early failure detection system for a multiprocessor system, two processors are connected to an input/output unit and a test circuit through two switches. More specifically, when one processor is connected to the input/output unit, the other processor is set in the standby mode and connected to the test circuit.
However, in such a system, a processor can be tested only when it is in the standby mode, and an idling processor, that is, a processor waiting for a subsequent instruction cannot be tested. Therefore, when a processor fails during idling, the failure cannot be detected until the processor starts processing in accordance with a subsequent instruction. If the processing is related to the critical control of the system, the operation of the system is seriously undesirably affected.
When testing is to be performed for an idling processor using a conventional system, a complex test circuit is required. Also, it is difficult to detect a failure throughout a processor using a conventional system.